`include "../codigo/Registers.v"


module TRegisters();

    // Signs
    reg ena;
    reg enb;
    reg enc;
    reg clock;
    reg reset;

    // Address registers
    reg [4:0] addra;
    reg [4:0] addrb;
    reg [4:0] addrc;

    // Output wires
    wire [31:0] dataa;
    wire [31:0] datab;

    // Input register
    reg [31:0] datac;

    
    // --------------------------------------------------------------
    // Initial assignments
    initial begin
        
        reset = 1;
        clock = 1'b1;
        
        reset = 0;
        ena <= 1'b1;

        addrc <= 10;
        datac <= #1 3;
        enc <= 1'b1;

        datac <= #2 5;
        ena <= #3 0;

        addra <= 10;
        ena <= #10 1'b0;
        addra <= #10 10;
        ena <= #30 1'b1;
        addra <= #30 30;
        
        $monitor({"Cycle: %d; Clock: %d;\n",
            "Address A: %d | Enable A: %d | Data A: %d;\n",
            "---------------------------------------------------\n"},
            $time, clock, addra, ena, dataa);

        #40 $finish;

    end

    always begin
        #5 clock = ~clock;
    end
    
    // --------------------------------------------------------------
    // Loads up the register structures
    Registers Reg1(reset, ena, addra, dataa, enb, addrb, datab,
        enc, addrc, datac);

endmodule
